The present invention relates to digital data signal analyzers and more particularly to a digital data signal analyzer for performing a one to one transformation of all the data points in a first matrix to a second matrix.
In the areas of scientific research, image analysis, signal processing and the like, enormous amounts of data are produced. There is a critical need for sound, accurate and easy-to-use apparatus for analyzing these data. Often data are continually produced without stopping for such analysis. The result can be the production of large amounts of inferior data. Apparatus which would permit a user to study the mathematical patterns underlying the data would be of great help to determine the best next step in analysis and to draw meaningful conclusions from the data already gathered. Moreover, the studies offered by such an apparatus may reveal that better experimental designs can be devised and implemented effectively. Also, underlying properties of the data, not directly measurable, but related to the data being produced, may be studied, and predictions related to the scientific content of the data, and future data, become possible.
Cellular automata processors have been proposed as apparatus for satisfying the above described need for sound, accurate and easy-to-use apparatus for analyzing enormous amounts of data. Research in the application of cellular automata processors has been ongoing for some time and today is more active than ever. Interesting and promising new approaches based on cellular automata models have been proposed to solve a wide variety of physical and biological modeling problems, ranging everywhere from galactic structures to DNA sequences.
Early methods for performing data analysis involved the use of general purpose computers controlled by long and elaborate programs. The use of the general purpose computer in performing data analysis met with limited success due to the extremely long processing time required to process images with many data points or pixels. To overcome the extremely long processing times characteristic of the general purpose computer, special purpose processors were proposed which implement an algorithm, or formula specifically applicable to analyze data in the form of images. One controlled sequence or algorithm which lends itself to implementation by special purpose processors is called cellular logic operations. These special purpose processors consider the input data as an M by N array of 0s and 1s representing black or white picture elements. From the input array another M by N array is derived wherein each point in the second array is a function of the state of the equivalent point in the initial array and a neighborhood of points surround it. The derivation of the other M by N array according to the mathematical technique implemented by the special purpose processor is called a transformation. A series of these transforms may be performed to determine some of the characteristics of data patterns displayed in the initial array.
The following are representative of various prior art special purpose processors for performing data analysis: U.S. Pat. Nos. 4,167,728; 4,174,514; 4,484,346; 4,395,698; 4,464,788; and 4,369,430.
U.S. Pat. No. 4,167,728 discloses a serial chain of substantially identical neighborhood transformation modules. The image data, generally in the form of raster scan lines, is serially shifted through a neighborhood extraction portion in each stage for sequentially accessing substantially all of the neighborhoods in the image matrix. Depending on the states of the pixels contained in the neighborhood extraction portion, certain transformations are performed and the transformed output is passed on to the input of the succeeding stage. A central controller which is coupled to all of the stages defines all of the particular transformations to be performed in the stages.
U.S. Pat. No. 4,174,514 discloses a technique by which the image data are partitioned and fed through associated parallel processors making up each stage.
U.S. Pat. Nos. 4,395,698; 4,369,430; 4,464,788 and 4,484,346 generally disclose neighborhood transformation logic circuitry for an image analyzer system which employs one or more neighborhood transformation stages. The stages operate to access groups of neighboring pixels in an image matrix, analyze them and generate a transformation output as a result of their analysis. Each stage includes logic circuitry that is programmable from a central controller to control the transformation process.
The above described special purpose processors have various disadvantages. For example, serial chains of processors are simple in structure but are slow in processing speed. The addition of a central controller increases the complexity of serial processor chains and adds to the processing times. Parallel processors that operate on partitioned data have fast processing speeds but are highly complex in structure. Still further, algorithm circuitry must be replicated in every processor in a parallel processor system. Therefore, for reasonably large arrays, such as 1000.times.1000, the parallel processor system would be very large and costly.
The present invention solves the above described disadvantages by providing a fast, accurate, inexpensive and easy-to-use apparatus for analyzing data. The present invention can be used, for example, in systems for performing image analysis, pattern recognition, signal processing, and the like.